|
Roadmap developing a 1,04 GHz - 4 (x v4) - segment delayline detector providing a time resolution of about 50 ps
Surface Concept will develop in 3 steps a fast delayline detector capable of a count rate acquisition of 1.04 GHz. The principle of the current detector will be kept, position information is gathered by time difference measurements, while each event can be assigned to an absolute time measurement referenced to an external reference signal. The precision of time reference measurements will be about 50 ps or smaller, while the difference measurements for spatial resolution should be done at an accuracy of about 25 ps. In two intermediate steps we will produce miniaturized detector versions which are photo-lithographically manufactured to work at 15 MHz count rates for the first and 260 MHz for the second development step reaching a time resolution of 80 ps or below. The outcome solution of the second step will be stabilized in phase 3, the time resolution will be improved to 50 ps or below further and a high count rate 4-fold detector is build up from 4 indepentend detector/readout units. This 4 segment solution may count up to 1.04 GHz on events at the hole active area, sorted by position and time to a large histogram based memory unit transferable block transfers to a PC. Further cascading can be done without many efforts.
All developments are compatible to the Surface-Concept- multi-mode segmentation for the use in electron analyzers.
Step 1: 15 MHz :
A non-segmented delayline detector with a typical loop transfer time of about 400 ps enables position encoding at 1000 x 1000 pixels at an active area of 20 mm x 20 mm. The time coordinate will be resolved using 12 bit dynamics (4096 channels at 80 ps resolution each). The max. travel time of pulses at the delay wires will be limited to about 40 ns. The read-out unit consists of 5 analogue time measurement modules followed by 65 MHz ADC´s which are coupled to a FPGA. This unit may be linked to a computer using a USB2.0 interface like done at our in spring 2004 available solution. One of the read-out channels is used for time reference measurements, the other 4 provide the position determination. All 5 measurements are needed to determine each event, so the electronics is limiting this solution to 65MHz, but the max. travel time at the delay lines would not enable this count rate. Therefore, the USB2.0 interface is still suficient (480 Mbit/s) for direct data transfer, the max. transferable count rate will be limited to 15 MHz, because each event needs a transfer of 4 bytes to the computer.
. Step 2: 260 MHz :
The photolithographically manufactured detector of step 1 will be redesigned to use loop transfer times of 205 ps, while the read-out distinguishes between left and right half of each both delaylines, the unit will be carried out 4 times building a virtual 4 fold segmentation. An event time sorting logic decides to supply the 4 read out lines with pulses originating from the 4 quadrants of the physically unsegmented detector. The electronics consists thus from 17 channels each equipped with a 65 MHz ADC (4 x 4 ch for position, 1 ch for time encoding). The event distribution will be done by means of a ultra-fast logic unit beeing already under development at Surface Concept today. The smaller loop transfer time enables max. travel times at the delay lines of 20 ns, e.g. 10 ns per each half delayline, therefore all quadrants may be read out with max. 65 MHz. Thus, the concept enables count rates up to 260 MHz with a position encoding by 512 x 512 pixels at a active area of 20mm x 20 mm. Again, the 17 channel unit is coupled to a FPGA, but not direct transfer to the PC will take place. The FPGA sorts all results into a 256 MByte histogram memory, organized as x,y,t such as a 3D dimensional array of - for example - 9 bits x 9 bits x 9 bits having a 2 byte dynamics (memory cell depth). The number of time channels might be organized to higher resolution at the cost less position channels. The USB2.0 interface still handles the block transfers from the histogram memory into the PC.
Step 3: 1.04 GHz :
The multi-channel scheme of step 2 will be integrated in an ASIC design mainly to enable kaskading of this solution. At the same time, the time resolution for position encoding should be improved to about 25 ps.
Adaptions of pulse widths an propagation dispersion are needed in MCP's and electronics matching the 25 ps resolution. MCP´s providing 350 ps native pulse width at 2 µm channel size are planned to use (www.burle.com), the analogue amplifieres will be exchanched by moduls working at bandwidths in the GHz region. The design of the detector itself has to be chanched to the needs of small pulse widths and loop dispersion as well as wire distance must match high count rates resulting in pulse handlings at <=2 ns overall FWHM without changes in the functional principle of the delayline detector. A thick film technique will be exploited to produce a 4 fold delayline detector working at this optimized parameters. The active area of all 4 detector segments might be scaled together and should reach in maximum 40 mm x 40 mm. Smallest active areas are expected at about 10 mm x 10 mm resulting in a position resolution of about 10 µm. The total nuber of pixels for this solution may be 1024 x 1024. Further cascaded designs of more segments are possible to produce in the same way. The 260 MHz read-out unit will be used four times (max. 1.04 GHz), another processor controls the data transfer from all four 256 MByte histogram memories into the PC using a still to determine transfer interface.
Notes concerning data acquisition:
The measured results of the four 260 MHz segments are stored in separeted histogram memories organized in 3D (x,y,t). It makes sense to define a flexible organization of the memories, such as (8 bit x 8 bit x 10 bit), (7 bit x 7 bit x 12 bit), (6 bit x 6 bit x 14 bit), or (5 bit x 5 bit x 16 bit) at 4 Byte memory cell depth and to include the option of a free selectable binning of the time channels. The option providing max. position resolution enables therefore 1024 x 1024 pixels with 4 Byte pixel dynamics at very long acquisition times into the histogram memery at at the count rate of 1 GHz.
|
Our partners in this process:
We are working together with strong, responsible, and well established partners on the way of this roadmap. This network of active and passive links bundels many skills, expertises and the special knowledges at different fields.
|
|
